1. Field of the Invention
The present invention relates generally to a communication system, and in particular, to an interleaving apparatus and method for a radio communication system. Specifically, the present invention relates to an interleaving apparatus and method that can be used to generate interleaving addresses and determine interleaver size such that interleaver memory efficiency is improved.
2. Description of the Related Art
Interleaving, a technique typically used to increase the performance of an error correction code in a fading channel, is closely associated with decoding of a random error correction code. Many applications, such as an air interface for International Mobile Telecommunication-2000(IMT-2000) requires a well established method for implementing various interleaving techniques. In addition, such technologies further serve to improve the reliability of digital communication systems, and in particular, performance improvements for existing and future digital communication systems.
The IMT-2000 standard recommends using a bit reverse interleaver for a channel interleaver. However, this interleaver can have various sizes, and the forward link and the reverse link defined by the IMT-2000 standard can have various types of logical channels. Therefore, in order to provide the ranges of the IMT-2000 standard, an increased memory capacity is required for the interleaver memory. For example, in an N=3 forward link transmission mode, interleavers with various sizes, such as between 144 bits/frame to 36,864 bits/frame, can be used. A brief description of the bit reversal interleaver is presented below.
In FIG. 1, a block diagram illustrates a permutation method of the bit reversal interleaver. Referring to FIG. 1, bit reversal interleaving is a technique for generating an interleaving address by exchanging bit positions from the most significant bit (MSB) to the least significant bit (LSB) of an address. This interleaving method includes a number of advantages. First, since the interleaver can be implemented using an enumeration function, it is simple to use the memory and it is easy to implement interleavers with various sizes. In addition, the bit positions of the permutated sequence are distributed at random in major locations. However, an interleaver having a size which cannot be expressed in terms of a power of 2 has low memory efficiency. For example, in order to implement a 36,864-bit interleaver, a 64 Kbit (65,536=216) memory is required. This is because the largest integer which can be expressed in terms of a power of 2 among integers smaller than 36,864, is 65,536. Therefore, 28,672 (65,536−36,864) bits are unused in the interleaver memory, thereby causing a memory loss. In addition, even though the memory has a sufficient capacity, it is very difficult to implement a method for transmitting the symbols. Further, it is difficult for a receiver to detect accurate positions of the received symbols. Finally, since various types of interleavers are used, it is necessary to store various interleaving rules in memory thereby requiring a controller, such as a central processing unit (CPU), to have a high memory capacity as well.
Conventional interleaving methods have a number of additional disadvantages as well. First, in existing interleaving methods, the size of the interleaver cannot be expressed in terms of a power of 2, and the interleaver having the largest size has the lowest memory efficiency level. That is, in designing an interleaver for an IMT-2000 forward link, the size of each logical channel is not expressed in terms of 2m, and the interleaver has a large size. Therefore, it is inefficient to use the bit reversal interleaving method.
Second, in existing interleaving methods, it is typically necessary to store various interleaving rules, or instructions, according to the interleaver sizes in the controller, CPU or host of a transceiver. Therefore, the host memory requires separate instruction storage in addition to an interleaver buffer.
Third, if the size of the interleaver is set to 2m in order to use the bit reversal interleaving method, it is necessary to delete unnecessary invalid addresses. Therefore, the interleaver has a complex transmission method and has difficulty in acquiring symbol synchronization during realization.
Accordingly, a need exists for an interleaving apparatus and method which provides a memory efficient interleaver which can use a bit reversal interleaving technique without undue complexity.